The functional blocks of a pipelined circuit have different throughput given the differences in the functions performed and differences in the input data processed by each functional block. In order to maximize the performance of asynchronous circuits, it is desirable to minimize the duration for which any of the functional blocks is kept waiting for input from any other of the functional blocks, and to minimize the duration for which any of the functional blocks is kept waiting to provide output to any other of the functional blocks.
FIFO buffers are often used between the functional blocks of a design in order to accommodate differences in throughput and variations in input data rates. One of the challenges in using FIFO buffers in a design is choosing suitable sizes for the FIFO buffers. A single size for all FIFO buffers would be unsuitable in view of the differences between the functional blocks. If a FIFO buffer is too big, it unnecessarily occupies too large a circuit area. If a FIFO buffer is too small, a functional block may have to wait for input data or wait to output data. For a design having a large number of pipelined functional blocks, the task of selecting suitable sizes for the many FIFO buffers may be difficult and time-consuming.
The present invention may address one or more of the above issues.